The present invention relates to a semiconductor device and a testing method of the same, and more particularly, relates to a semiconductor device composed of large scale integration type memory cell array and a testing method of the same capable of carrying out a testing effectively.
As a level of integration in semiconductor devices including a memory device has improved, a testing time of the semiconductor device has increased. Accordingly, one of the important problems to be solved in the development of semiconductor devices is how the testing time of the semiconductor device can be reduced.
Namely, as high integration of semiconductor device is achieved, it is required that various testing methods are effectively conducted to obtain reliable test data in short time. Examples of the testing methods are insulation failure, current leakage, burn-in test to check presence of parasite volume or parasite transistor and hold test to confirm a refresh cycle.
As the methods, it is developed, for example, that circuit construction is built in the semiconductor device, or that the circuit construction is provided in external and peripheral parts of the semiconductor device. The above problem causes in such products that a plurality of cell data is selected by one column address and is assigned to input/output means (I/O) different from each other, because bit map is complicated in a large scale integrated semiconductor device generally called as CPF type memory cell array of which example is shown in FIG. 8.
For example, when the HOLD test to disturb a cell is done, a pattern worse to the observing cell is written in the cell. It is different from each other by a sort of disturbance to be applied and is generally called as physical pattern because it is the pattern written based on physical consideration without any relation to address order. That is, the physical pattern means, where semiconductor device is tested, a predetermined pattern to be written in specific cell of the semiconductor device for obtaining testing data.
A product using a semiconductor device which has thirty-two or sixteen of an output/input terminals is tested in a test mode called as I/O compression in its wafer test or burn-in test. According to the test mode, read-out and write-in is carried out by using one or several units of the input/output terminals selected from thirty-two or sixteen of I/O pins which are input/output means of semiconductor device to be tested.
In other words, instead of the conventional test method that all of input/output means (i.e. I/O pins) are used to check output to input, the test mode includes selecting one or several I/O pins from a plurality of the I/O pins and inputting certain test data into the selected I/O pin(s) to check its output conditions, whereby it is decided if product quality of the semiconductor is satisfied with the predetermined standard.
In more detail, the predetermined test data is input in only one I/O pin to output the predetermined data in each of plural bit lines (write buses, WBST) , simultaneously. That is, the output conditions of plural bit lines corresponding to the I/O pins other than the one I/O pin are simultaneously tested by using one of the I/O pins.
If the number of the input/output terminals (i.e. I/O pins) is reduced, the limited number of the I/O pins provided in the test board to be used in the testing operation can be assigned to more tips, and therefore, the method is essential in the field, because more tips can be checked at a time and test efficiency is more effective. In the above compression test mode, for example, if only one input/output terminal is selected and xe2x80x9c11xe2x80x9d data is written in the terminal, the situation at the time is same as that xe2x80x9c1xe2x80x9d data is written in the other I/O terminals not to be selected.
Accordingly, such the test method is generally called compression test method. A method for writing the physical pattern is, for example, disclosed in Japanese Patent Application Laid-Open No. 9-147597(147597/1997). According to the conventional method, certain cell is selected by using an address information, because cell data existed in certain address position of memory arrays in semiconductor device is inverted.
However, there are disadvantages in the conventional method that load becomes more and calculation processing speed is lowered, because the address signal is used.
Also, the technology that the cell is selected by using the address information is disclosed in Japanese Patent Application Laid-Open Nos. 5-249196(249196/1993) and 10172298(172298/1998), but there is same problems as above.
It is disclosed in Japanese Patent Application Laid-Open No. 7-12900(12900/1995) that a test pattern generating unit and an exclusive pattern generating unit which generates an address for writing test results to fail memory are disposed independent of semiconductor device to be tested. However, the operations are complicated because the units are disposed separate from the semiconductor device to be tested and are reconnected with the semiconductor device at every time when the semiconductor device to be tested is changed, and the same problem as above also exists.
On the other hand, an indication method of fail bit map is disclosed in Japanese Patent Application Laid-Open No. 9-91999(91999/1997), but such technology that circuit construction capable of writing particular physical pattern without using address information in semiconductor device to be tested is not disclosed.
Therefore, it is an object of the invention to provide an improved semiconductor device in which simple circuit construction is incorporated.
It is another object of the invention to provide construction of high integration type semiconductor device using particular physical pattern without address data, by which memory cell arrays are accurately and effectively tested in short time.
It is a still another object of the invention to provide a testing method of the semiconductor device capable of checking the memory cell arrays in compression mode for a short time, accurately and effectively.
The present invention provides a circuit and method for converting write data generated by the write data bus, considering the polarity of each memory cell, when the write data applied to one input terminal is written into a plurality of memory cells simultaneously. The data is written considering the polarity of each memory cell such that the same phase data are stored in the plurality of memory cells connected to the intersection of bit lines and selected word lines.
According to one feature of the invention, a semiconductor device comprises memory cell arrays in which memory cells disposed in intersection of bit lines and word lines are arranged in a matrix; an input terminal to which a pattern signal is input when a compression test is conducted; input buffer means connected to said input terminal for outputting said pattern signal supplied from said input terminal to one of plural write data buses; a write circuit for writing said pattern signal data into said memory cells through said write data buses; first switches that selectively connect said one of plural write data buses to others of the plural write data buses; and a control unit for controlling said first switches in response to a compression test entry signal which starts the compression test.
According to a second feature of the invention, a testing method of semiconductor device comprises the steps of: testing a semiconductor device including memory cell arrays in which memory cells disposed in intersection of bit lines and word lines are arranged in a matrix, selecting one line for inputting test pattern and plural lines for not inputting the test pattern from at least one of bit lines and word lines; activating the physical pattern generating means [means for selecting input terminal of test pattern which select if a test pattern predetermined for specific tests of the semiconductor is inputted or not in each terminal of plural lines selected from at least one of bit lines and word lines]; and means for generating physical pattern which is composed so that the predetermined data is outputted in each data buses connected to the other plural lines, when the certain data is inputted in the lines selected to input the test pattern and the certain data is outputted in the data buses connected to the lines.
The semiconductor device of the invention adopts the basic technology construction and so, the predetermined particular physical pattern can be written in certain cells, where the products, such as process products using CPF type cells, in which bit map is complicated are checked by wafer tests or other tests which need bit compression, and the address information is not necessary unlike conventional technology.
Accordingly, according to the invention, accurate testing can be done by simple change of circuit without affecting address signals.